Roofline

What is Roofline?

Roofline is an edge AI deployment stack: a compiler, a device runtime and benchmarking tools for getting trained models running on the CPUs, GPUs and NPUs inside shipping hardware. The target is edge hardware in industrial, automotive, robotics and mobile products, where fragmented hardware and software stacks can make deploying new AI models slow and engineering-intensive.

The company was founded in 2024 as a spin-off from RWTH Aachen University in Germany.

How it works

The compiler is built on MLIR and IREE. Models from major AI frameworks and formats, including PyTorch, TensorFlow and ONNX, are lowered through layered intermediate representations into executables tuned for a specific hardware backend, rather than converted by a per-chip toolchain written by hand. A lightweight runtime then executes the compiled model on the device and orchestrates work across the SoC, so a workload can run heterogeneously across CPU, GPU and NPU.

That architecture is the argument. Supporting a new chip or a new model normally means model- and hardware-specific engineering that does not carry over to the next one. A retargetable compiler is meant to make that work reusable, which is where the claimed reduction in duplicated effort comes from.

Position in IREE

Roofline holds the chair of the IREE Technical Steering Committee. IREE is a sandbox-stage project of the LF AI & Data Foundation, and as of September 2026 its CONTRIBUTING.md lists eight voting TSC members: six from RooflineAI, including chairperson Maximilian Bartel, and two from AMD. For anyone weighing a dependency on IREE, that is a checkable fact about who steers it.

Hardware support

Published on the Roofline site as of September 2026:

• CPU: ARM Cortex-M, ARM Cortex-A, ARM SVE, Apple Silicon, Qualcomm Oryon, Qualcomm Kryo, Google Tensor, AMD x86-64, Intel x86-64, RISC-V
• GPU: ARM Mali, ARM Immortalis, Qualcomm Adreno, Apple Silicon GPU, Nvidia RTX family
• NPU: NXP eIQ Neutron

Roofline additionally lists RISC-V RVV, RISC-V VME, ARM SME and Qualcomm Hexagon as supported. Several targets carry a published case study.

Model support

The compiler is described as architecture-agnostic, covering CNNs, RNNs, LLMs, VLMs, MoE models and VLAs. The site's supported-model list spans LLM, vision, language, audio and radar workloads, naming Liquid AI LFM2.5, Gemma 3, Qwen 3, Llama 3.2, Phi-2, YOLO, ResNet, MobileNet, Whisper and others.

Two recent pieces of work are documented rather than asserted. In June 2026 Roofline published a case study adding native mixture-of-experts support to its IREE-based stack, compiling IBM Granite 3.1 1B-A400M, Liquid AI LFM2-8B-A1B and Qwen-REAP-15B-A3B end to end. In July 2026 it showed day-0 support for Liquid AI's LFM2.5-230M running on the CPU and eIQ Neutron NPU of NXP's i.MX 95.

There is also a May 2026 paper on vector-length-agnostic code generation for Arm SVE, reporting up to 1.5x over IREE's existing NEON path and up to 3.4x when scaling from 128-bit to 512-bit SVE in a cycle-level simulation.

Pricing

No public price list. Roofline describes its commercial arrangement as a subscription that scales with usage, quoted through sales. The site's licensing page splits access into a non-commercial tier (unlimited developer access inside an organisation, coverage for selected models, documentation and stability guarantees) and a commercial tier that adds deployment to customers, guaranteed coverage for TFLite, PyTorch and ONNX models, continuous optimisation work and premium support.

Who should use it

Chip and IP vendors, and product teams, that need to deploy a broad range of AI models across CPUs, GPUs and NPUs without rebuilding the software stack for every new model or hardware target. The concrete cases: an SoC with an NPU whose vendor toolchain covers a subset of the models you need, or a product line spanning several chips where each one currently means a separate deployment path. Roofline's argument is that reusable compiler infrastructure gives broad model and hardware coverage while keeping performance across targets.

Roofline addresses a different deployment problem from tools such as llama.cpp, Ollama and vLLM. Those run models through established CPU and GPU execution paths, mostly on developer machines or servers, and are open source. Roofline builds compiler and runtime infrastructure for deploying across heterogeneous edge hardware, including NPUs, and is commercially licensed. Teams that need a model running on a laptop this afternoon want the former; chip vendors and product teams facing a bring-up across several hardware targets are the ones this addresses.